This ebook constitutes the refereed lawsuits of the tenth foreign Workshop on strength and Timing Modeling, Optimization and Simulation, PATMOS 2000, held in Göttingen, Germany in September 2000.
The 33 revised complete papers offered have been rigorously reviewed and chosen for inclusion within the publication. The papers are geared up in sections on RTL strength modeling, energy estimation and optimization, system-level layout, transistor point layout, asynchronous circuit layout, strength effective applied sciences, layout of multimedia processing functions, adiabatic layout and mathematics modules, and analog-digital circuit modeling.
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