By Prashant Saxena, Rupesh S. Shelar, Sachin Sapatnekar
This quantity offers a whole realizing of the elemental reasons of routing congestion in present-day and next-generation VLSI circuits, deals thoughts for estimating and relieving congestion, and offers a severe research of the accuracy and effectiveness of those recommendations. The e-book comprises metrics and optimization ideas for routing congestion at a number of levels of the VLSI layout stream. the topics coated contain a proof of why the matter of congestion is necessary and the way it's going to pattern, plus definitions of metrics which are applicable for measuring congestion, and outlines of thoughts for estimating and optimizing routing congestion concerns in cell-/library-based VLSI circuits.
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