By Xinmiao Zhang

Error-correcting codes are ubiquitous. they're followed in virtually each sleek electronic conversation and garage approach, reminiscent of instant communications, optical communications, Flash stories, machine demanding drives, sensor networks, and deep-space probing. New-generation and rising purposes call for codes with greater error-correcting strength. nonetheless, the layout and implementation of these high-gain error-correcting codes pose many demanding situations. and they contain advanced mathematical computations, and mapping them on to usually ends up in very excessive complexity.

VLSI Architectures for contemporary Error-Correcting Codes

serves as a bridge connecting developments in coding concept to sensible implementations. rather than targeting circuit-level layout strategies, the e-book highlights built-in algorithmic and architectural modifications that result in nice advancements on throughput, silicon sector requirement, and/or strength intake within the implementation.

The aim of this publication is to supply a complete and systematic assessment of obtainable strategies and architectures, for you to be simply via process and designers to advance en/decoder implementations that meet error-correcting functionality and value requisites. This booklet should be extensively utilized as a reference for graduate-level classes on VLSI layout and error-correcting coding. specific emphases are put on challenging- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. those codes are one of the best applicants for contemporary and rising purposes as a result of their stable error-correcting functionality and decrease implementation complexity in comparison to different codes. to assist clarify the computations and en/decoder architectures, many examples and case stories are included.

More importantly, discussions are supplied at the merits and downsides of alternative implementation techniques and architectures.

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